发明名称 Interpolating digital to analog converter architecture for improved spurious signal suppression
摘要 A digital-to-analog conversion method and interpolating digital-to-analog converter (20) for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage (22) converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage (26) converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output (28) to an interpolation stage (30) which provides an interpolated output (32) at an interpolation output rate. A feedback circuit (34) provides the interpolated output to an input of the second conversion stage (26). <IMAGE>
申请公布号 EP0790708(A2) 申请公布日期 1997.08.20
申请号 EP19970101555 申请日期 1997.01.31
申请人 HARRIS CORPORATION 发明人 MYERS, BRENT A.
分类号 H03M1/08;H03M1/68;H03M1/80;(IPC1-7):H03M1/08 主分类号 H03M1/08
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