| 摘要 |
<p>PURPOSE:To synchronize a video signal with a sampling clock in spite of a phase error between a horizontal synchronizing signal and the video signal, by generating plural video signals with different delay quantities, and finding the deviation of a phase directly based on phase relation between those signals and two sampling clocks with different phases. CONSTITUTION:A supplied video signal is separated to an FVIDEO to be inputted to an FF7 as it is, an LVIDEO to be inputted to an FF6 after delay of 4.17ns being given at a delay circuit 3, and a BVIDEO to be inputted to an FF5 after being added at the delay circuit 3 and a delay circuit 4 and delay of 8.31ns being given, and its phase state is detected by the leading edge of the sampling clock outputted from a sampling clock selection circuit 9. A phase decision circuit 8 outputs an F signal from inputted BDATA, FDATA, and LDATA to the sampling clock selection circuit 9. The sampling clock selection circuit 9 switches the sampling clock by an inputted F signal.</p> |
