发明名称 ENZANSOCHI
摘要 PURPOSE:To obtain an arithmetic unit consisting of super-parallel processors wired with light by providing plural parallel computing elements where processors, light emitting elements, and light receiving elements are wired and arranged in one to one and a wiring means which makes the exit light of a light emitting element incident on a light receiving means on another plane. CONSTITUTION:The light emitted from an array light source 2 on an input face 3 is deflected by an optical connection face 11 and is condensed on a light receiving element array 5 on an intermediate face 7. The reception signal light is photoelectrically converted and is switched by the cross path switch of a switch array 4 to drive an array light source 6. The light reaches a light receiving element array 9 on an output face by repeating the same procedures to connect many processors 8. The pitch of array light sources is defined as (a), and respective stages are equally divided by a prescribed rule, and lenses are arranged by a prescribed rule. When the distance between the input face 3 and the output face 10 is defined as (b) and respective stages are arranged at prescribed intervals, light is diffracted, refracted, and reflected in accordance with a prescribed wiring rule and the exit light is condensed on light receiving elements.
申请公布号 JP2643521(B2) 申请公布日期 1997.08.20
申请号 JP19900046319 申请日期 1990.02.27
申请人 NIPPON DENKI KK 发明人 KAWAI SHIGERU
分类号 G06E1/00;G06F15/16;G06F15/173;G06F15/80;H04B10/11;H04B10/112;H04B10/80;H04Q3/52 主分类号 G06E1/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利