发明名称 |
VLSI circuit structure for implementing JPEG image compression standard |
摘要 |
A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024x1024 color images.
|
申请公布号 |
US5659362(A) |
申请公布日期 |
1997.08.19 |
申请号 |
US19940302110 |
申请日期 |
1994.09.07 |
申请人 |
UNIVERSITY OF SOUTH FLORIDA |
发明人 |
KOVAC, MARIO;RANGANATHAN, NAGARAJAN |
分类号 |
H04N7/30;G06T1/20;G06T9/00;H04N1/41;(IPC1-7):H04N7/32 |
主分类号 |
H04N7/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|