发明名称 GAKUONSHINGOSHORISOCHI
摘要 A series of delay circuits are provided which receive tone signal sample data of plural channels supplied on a time shared basis, hold plural tone signal sample data of each channel and hold these plural sample data while sequentially delaying them. The series of delay circuits are connected in an endless manner to form a circulating loop and plural data selection circuits are provided at predetermined delay stages. Each data selection circuit performs a selection control as to whether new tone signal sample data should be loaded in the delay circuit loop or data in the delay circuit should be circulated. Tone signal sample data which are provided sequentially from the delay circuit loop after delay are sequentially operated with filter coefficients of plural orders and results of the operation are accumulated to obtain a filter operation output. This construction enables tone signal sample data of a necessary channel to be loaded in the delay circuit loop at a point of a necessary data selection circuit in a time period which is shorter than one cycle of the entire delay circuit loop. Therefore, the time division period of supplied tone signal sample data of each channel can be made different from the time division period of each channel in the delay circuit loop.
申请公布号 JP2643553(B2) 申请公布日期 1997.08.20
申请号 JP19900194019 申请日期 1990.07.24
申请人 YAMAHA KK 发明人 SUZUKI HIDEO;OKAMURA KAZUHISA
分类号 G10H1/12;H03H17/00;H03H17/02 主分类号 G10H1/12
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