发明名称 |
Pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid |
摘要 |
The power consumed by a cache memory when the cache is read is reduced by utilizing a cache access circuit to prevent the cache from being read when the information stored in the cache is invalid, such as when the processor is powered up, reset by a user, or an invalidation bit is set.
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申请公布号 |
US5659712(A) |
申请公布日期 |
1997.08.19 |
申请号 |
US19950452659 |
申请日期 |
1995.05.26 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
DIVIVIER, ROBERT J.;BIGNELL, ROBERT |
分类号 |
G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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