发明名称 |
Device for controlling memory data path in parallel processing computer system |
摘要 |
A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.
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申请公布号 |
US5659687(A) |
申请公布日期 |
1997.08.19 |
申请号 |
US19960634635 |
申请日期 |
1996.04.18 |
申请人 |
ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
KIM, SEONG-WOON;YOON, SUK-HAN;WON, CHUL-HO |
分类号 |
G06F13/16;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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