| 摘要 |
In a data processing system, a tag memory is divided into a first tag memory portion and a second tag memory portion. Next, an address for recalling requested data is generated by a central processing unit. Thereafter, a first and second tag memory addresses are concurrently computed, where the first and second tag memory addresses have bits which differ in value in a selected corresponding bit location. In response to the value of the bit in the selected bit location, the first tag memory address is coupled to either the first or second tag memory portion, and, concurrently, the second tag memory address is coupled to the other tag memory portion. Next, tag data is concurrently recalled from both the first and second tag memory portions utilizing the first and second tag memory addresses. A search tag is generated in response to the memory address from the CPU. Thereafter, the search tag and the recalled tag data from the first and second tag memory portions are concurrently compared. If either comparison results in a match, a "hit" is indicated. In response to the indication of a hit, requested data is recalled from the data portion of the cache memory system utilizing the recalled tag data that matched the search tag.
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