| 摘要 |
A filter uses a digital integrator that establishes the sum, weighted by a coefficient B, of q1-bit input data arriving at a frequency F. The integrator includes a first p-bit shift-right register; a second q-bit shift-right register, circularly connected and storing the current input data in its most significant bits; and a full bit adder having two inputs respectively connected to the outputs of the first and second shift registers, and an output connected to the input of the first shift register. A sequencer enables the shifting of the first register during p clock cycles, and the shifting of the second register during q clock cycles starting b cycles after the beginning of the p cycles, number b being selected as a function of coefficient B.
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