| 摘要 |
PURPOSE:To offer a delay circuit which can delay the high speed digital in an optical bit unit. CONSTITUTION:A high-order bit counter 105 and a low-order bit counter 106 count the clock signals received from a timing signal generating circuit 107 and input the column and row addressing signals respectively to a DRAM 109 via a multiplexer 108. The DRAM 109 outputs an address signal (h) corresponding to the preceding addressing signal and also writes a signal (g). When the counted values of both counters 105 and 106 reach the set levels of dip switches 101 and 102, a comparator 104 resets both counters 105 and 106. These operations are repeated so that the signal (g) is delayed in accordance with the set levels of switches 101 and 102 respectively. |
