| 发明名称 |
CHENKAIRO |
| 摘要 |
A delay circuit comprising a plurality of cascaded saturating circuit elements is provided. The delay circuit may be incorporated in such circuits as modulators and demodulators to provide signal delay. |
| 申请公布号 |
JP2639390(B2) |
申请公布日期 |
1997.08.13 |
| 申请号 |
JP19850149096 |
申请日期 |
1985.07.05 |
| 申请人 |
HYUURETSUTO PATSUKAADO CO |
发明人 |
RICHAADO EI BAUMUGAATONA;JON ENU DEYUUKUSU;JOOJI EI FUITSUSHA |
| 分类号 |
H01L21/8234;G01S7/52;H01L27/06;H01L27/088;H03H11/26;H03K5/00;H03K5/13;H03K7/06;H03K7/08 |
主分类号 |
H01L21/8234 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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