Bus routing circuit

摘要

A bus switch (40) providing versatile data path routing between a first group of buses (10) associated with a disk array controller and a second group of buses (20) associated with the individual disk drives within the disk array includes a plurality of bus multiplexers (141-146), equal in number to the number of drive buses. Each bus multiplexer (141-146) includes a plurality of inputs, each input being connected to a corresponding one of the controller buses. The multiplexers (141-146) are responsive to select and enable signals to connect selected controller buses to selected drive buses. The bus switch (20) additionally includes a plurality of bus multiplexers (151-154) for directing data from the drive busses to the controller busses. A parity generator (50) is coupled to the controller buses and to a further multiplexer (155) in the bus switch (20). The output of the parity generator (50) is also provided to each of the multiplexers (141-146;151-154) and can be directed thereby to any of the controller or drive buses.