HANDOTAISOCHI

摘要

A semiconductor memory device which has a memory portion and a counter to count rows and/or columns of the memory portion, the counter being so constructed to return to a reset mode at the beginning of an address counting sequence when coming up to an arbitrary address such that an address or addresses corresponding to a region of the memory containing one or more defective memory cells and occurring after the arbitrary address are inaccessible. The counter thereby comprises a defective bit relief circuit built into the memory device.