| 摘要 |
PCT No. PCT/EP95/01455 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Apr. 18, 1995 PCT Pub. No. WO96/33456 PCT Pub. Date Oct. 24, 1996A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units. |
