| 摘要 |
A circuit controlling the transmission of information from a testing probe to an ICE TM base unit for debugging an electronic component having a dedicated bus. The circuit comprises a plurality of gate arrays coupled together to operate in a pipeline fashion. Each of the plurality of gate arrays includes a bus tracking component, a formatting component, filtering circuitry and address translation circuitry. The bus tracking component monitors the dedicated bus and transfers internal command signals to its associated formatting component and formatting components of the other gate arrays. The formatting component transfers only completed data to the ICE TM base unit for tracing. If in "Format" mode, the formatting component synchronously aligns the completed data and its associated addressing information before transferring such information to the ICE TM base unit. In "Raw" mode, however, information from the electronic component is immediately transferred to the ICE TM base unit without alignment. The filtering circuitry enables selective tracing of a type(s) of bus cycle(s) by signaling the ICE TM base unit whether or not to trace the frame during this particular bus cycle. The address translation circuitry calculates various address information required by the ICE TM base unit but is not transmitted by the electronic component to minimize required operations by word recognizers in the ICE TM base unit.
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