发明名称 |
Memory addressing circuit |
摘要 |
A memory addressing circuit allows data stored in consecutive addresses to be fetched simultaneously to improve the data transfer rate in a DRAM system. In addition, the consecutive data may extend across blocks. Specifically, the addressing circuit receives a signal indicating shift up or shift down as input to a predecoder circuit and supplies a CARRY or BORROW signal to a decoder. The decoder receives this signal, which enables it to access a block higher or lower than a block corresponding to an address designated by the original input address. <IMAGE>
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申请公布号 |
EP0788112(A2) |
申请公布日期 |
1997.08.06 |
申请号 |
EP19970300611 |
申请日期 |
1997.01.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MIYATAKE, HISATADA;YAMASAKI, NORITOSHI |
分类号 |
G11C11/413;G11C7/10;G11C8/04;G11C11/408;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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