发明名称 DEIJITARUDEETASHUNDANKENSHUTSUKAIRO
摘要 <p>PURPOSE:To provide the subject detecting circuit which can shorten the time when the digital date has a hit and then a data hit detecting signal is transmitted and also can work stably even with a low C/N ratio. CONSTITUTION:A frame synchronization protecting circuit (a synchronization detector 1, a coincident counter 2, a discordant counter 3 or a frame counter 4, etc.) protects the frame synchronizing signals produced by the frame synchronization patterns which are included in a prescribed cycle in the received digital data. Then a correlative pattern synchronization detector 9 is provided to the frame synchronization protecting circuit to detect the correlative discordance of the frame synchronization patterns and to produce a detection pulse together with a discordance detector 11 which produces a discordance signal based on the inverted signal of the detection pulse and the retrieving position pulse of the frame synchronization pattern obtained by the frame synchronization protecting circuit, and a circuit (a flip-flop 8) which receives the discordance signal and outputs a date hit detection signal.</p>
申请公布号 JP2639277(B2) 申请公布日期 1997.08.06
申请号 JP19920079282 申请日期 1992.02.29
申请人 NIPPON DENKI KK 发明人 OOYAMA TAKEKATSU
分类号 H04B14/04;H04L7/00;H04L7/08;(IPC1-7):H04L7/08 主分类号 H04B14/04
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