Memory cell configuration for increased capacitor area

摘要

A capacitor for use as a part of a memory cell, such as a DRAM, constructed according to design rules of 0.4 mu m, or less. The capacitor includes a cross-shaped capacitor electrode (50) connected to a memory transistor of the DRAM and may overlie bit lines (57) of the DRAM to provide a COB array. An insulation layer (52) overlies the memory transistor (56), and the cross-shaped capacitor electrode (50) in turn overlies the insulation layer. A dielectric layer (62) and a conformal capacitor electrode (60) are arranged with respect to the cross-shaped capacitor electrode to complete the capacitor. The cross-shaped capacitor electrode may be dimensioned to be about 0.2 mu m, or more, thick, 1.6 mu m long, 1.6 mu m wide, with each arm of the cross-shaped electrode about 0.4 mu m wide, wherein the lateral sides of the electrode contribute to a surface area of the capacitor electrode to increase the capacitance of the capacitor in which it is included.