发明名称 |
Repairable chip bonding/interconnect process |
摘要 |
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
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申请公布号 |
US5653019(A) |
申请公布日期 |
1997.08.05 |
申请号 |
US19950522471 |
申请日期 |
1995.08.31 |
申请人 |
REGENTS OF THE UNIVERSITY OF CALIFORNIA |
发明人 |
BERNHARDT, ANTHONY F.;CONTOLINI, ROBERT J.;MALBA, VINCENT;RIDDLE, ROBERT A. |
分类号 |
H01L21/58;H01L21/60;H01L21/68;(IPC1-7):H05K3/34 |
主分类号 |
H01L21/58 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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