| 摘要 |
PROBLEM TO BE SOLVED: To reduce a peak current related to all bit mats at the time of CBR (column address strobe before row address strobe) refresh operation of a DRAM. SOLUTION: This memory is provided with a CBR control circuit 78 detecting the CBR refresh operation. When CBR refresh is detected, the amplification of the bit mats MAT1, MAT2 are shifted each other, and the times when respective bit mats MAT1, MAT2 flow peak current through are made to alternate. In a form of another execution, when the CBR refresh is detected, word lines WL1, WL2 are shifted each other and made active, and thus, the times when respective bit mats MAT1, MAT2 pass the peak current through are made alternative. |
