Mask generator usable with addressing schemes in either big endian or little endian format

摘要

A mask generator for use with at least first and second addressing schemes in a microprocessor system, wherein a first addressing scheme is in little endian format and a second addressing scheme is in big endian format. The mask generator, based upon data input as to the number of bytes to be written and the byte address of the first byte, will generate a mask containing as many contiguous 1's as there are bytes to be written. The byte address is then used to rotate the generated mask to align it accordingly with respect to the position of the bytes within the portion of the word that is to be written. The mask generator employs a simple 1's complement together with a specially generated term K for the most significant bit of the mask output, and the rotator is constructed with 0, 2 and 4 bit rotates in a first stage, and 0, 1, 4 and 5 bit rotates in a second stage. This approach enables a single generated mask with appropriate rotation function to serve for both big and little endian address formats without requiring an adder to perform a 2's complementing operation.