发明名称 CLOCK GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the image quality of a display image in an image transmission system from being deteriorated. SOLUTION: A phase comparator 12 compares a count S18 of a counter with a system time reference value (SCR) at the point of input time of the SCR. An output signal S12 of the phase comparator 12 is smoothed by an LPF (low pass filter) 13 and used for original data to control a voltage controlled oscillator(VCO) 16. A register 14 uses a video blanking identification signal BL as a clock to update the content at the point of time when the video blanking is started. A D/A converter(DAC) 15 applies D/A conversion to the output signal S14 of the register 14 based on the clock S16 to provide an output of an analog signal S15 corresponding to the received control data. The conversion speed of the DAC 15 (that is, the period of the clock S16) is sufficiently higher than the period of the SCR, then the control signal given to the VCO 16 is changed to be a rectangular wave after rising of a blanking identification signal and the oscillated frequency of the VCO 16 is revised by this control signal. The clock S16 is succeedingly given to a counter 18, in which number of cycles is counted to prepare for the input of the succeeding SCR.
申请公布号 JPH09205564(A) 申请公布日期 1997.08.05
申请号 JP19960013121 申请日期 1996.01.29
申请人 OKI ELECTRIC IND CO LTD 发明人 NONAKA MASAHITO;FUKUI KIYOSHI;YOSHIDA TETSUO
分类号 H04N5/04;H03L7/093;H04N7/15;H04N7/24;H04N19/00;H04N19/423;H04N19/70;H04N19/80;H04N19/85 主分类号 H04N5/04
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