| 摘要 |
A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor. When the logic state on the output node is low, the feedback logic circuit generates a low signal, which activates the dynamic PMOS transistor into a conductive state, thus increasing the pullup strength of the logic structure. This increased pullup strength provides for an improved switching for the next logic state transition: low-to-high. Once the output node has transitioned to the logic high state, and after a fixed time delay, the feedback logic circuit generates a logic high signal, which turns off the dynamic PMOS transistor, which weakens the pullup strength of the logic structure. In view of this weakened pullup strength, the next logic state transition of the output node-high-to-low-is accomplished much faster.
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