Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp

摘要

A single clamp circuit for integrated circuits with multiple Vdd power pins by coupling the various Vdd busses to an ESD clamped Vdd bus or pseudo- Vdd bus via diodes. The diodes will provide coupling from any Vdd bus to the clamp circuit during a positive ESD transient. A diode for each Vdd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each Vdd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses. To help filter small signal noise and provide an additional charged device model discharge path, a capacitor is added from the pseudo or ESD Vdd to substrate ground. Also disclosed is an ESD protection scheme for allowing a pad voltage to exceed the power supply voltage without using an avalanching junction as the ESD protection means. Further disclosed is a clamp scheme for allowing the transistors of the power supply clamp to see voltages lower than that of the pad voltage which exceed the process reliability limits.