发明名称 VOLTAGE LEVEL CONVERSION CLOCK GENERATOR
摘要 PROBLEM TO BE SOLVED: To make the substrate of an information processor compact, light in weight and inexpensive. SOLUTION: This generator is provided with a PLL circuit 21 converting the input clock signal Ci having the one potential of the binary which are the same as the reference voltage Vi by an arbitrary frequency into a certain frequency and outputting a PLL output clock signal Cp. Further, the generator is provided with a voltage level conversion circuit 4 converting the PLL output clock signal Cp into the voltage level of an arbitrary purpose set by a voltage level control signal CTL for the reference voltage Vi and outputting an output clock signal Co.
申请公布号 JPH09205361(A) 申请公布日期 1997.08.05
申请号 JP19960012644 申请日期 1996.01.29
申请人 NEC GUMMA LTD 发明人 ISHIZAKA YASUHIRO
分类号 H03K5/02;G06F1/04;G06F3/00;H03K19/0175;H03L7/06;H03L7/16 主分类号 H03K5/02
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