发明名称 ASIC WITH BUILT-IN ARITHMETIC PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To easily apply a general purpose ICE to the debug, etc., of an ASIC 1 (application specific integrated circuit) by switching the control between control by a CPU core 2 and the control from the outside by a simple constitution, when a signal is transmitted. SOLUTION: In the control bus 10 provided between a CPU core 2 and a user circuit 3, in an address bus 11 and between data output bus 13 and data input bus 14 which are converted and connected in a unidirection, three-state buffers 8a to 8c and external terminals 7a to 7c are interposed, respectively, in order of the flowing directions of signals. When the user circuit 3 is controlled from the outside, the outputs of the three-state buffers 8a and 8b are inhibited by a bus control circuit 4, and the three-state buffer 8c switches the output/output inhibition by the control signal according to the input/output of data.
申请公布号 JPH09198273(A) 申请公布日期 1997.07.31
申请号 JP19960005958 申请日期 1996.01.17
申请人 SHARP CORP 发明人 ISHII YASUSHI
分类号 G06F11/22;G06F13/36;G06F15/78 主分类号 G06F11/22
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