SELECTIVE-ETCH EDGE TRIMMING PROCESS FOR MANUFACTURING SEMICONDUCTOR-ON-INSULATOR WAFERS

摘要

The peripheral edge of a semiconductor-on-insulator wafer is trimmed by forming a preferentially etchable masking layer over all but the edge margin of the surface of the semiconductor layer and selectively etching the semiconductor layer, preferably without etching either the masking layer or the insulating layer. The thickness, thickness variation, surface roughness and surface defects of the semiconductor layer approximate, before edge-trimming, the same characteristics of a wafer in its final, finished form which is suitable for device fabrication. As applied to bonded semiconductor-on-insulator wafers, the process removes lamination defects located between the semiconductor layer and the insulating layer. The edge-trimmed semiconductor-on-insulator wafer resulting from the method of the present invention is characterized by a semiconductor layer having a sharp peripheral edge. Bonded semiconductor-on-insulator wafers are further characterized by a lack of peripheral lamination defects.