发明名称 BIT SLICE TYPE MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To obtain a bit slice type memory device capable of monitoring a phase deviation even in the retained state of data in a buffer and restoring from an abnormal state by itself by periodically monitoring a phase deviation between upper and lower bits by using a monitoring cell. SOLUTION: A cell buffer part 10 is provided with a detection pattern inserting part 1 and a phase deviation detecting part 2 in addition to conventional constitution. When an input data processing part 11 detects a monitoring cell, the inserting part 1 inserts a phase deviation detection pattern into a phase deviation detection pattern area in the monitoring cell. Then output data from bit slice type memory parts 12, 13 are inputted to an output data processing part 14 and inputted also to the detecting part 2. The detecting part 2 checks the phase detection pattern at the time of detecting the monitoring cell, and when abnormality is detected, resets the buffers of the two memory parts 12, 13 to execute phase adjustment.
申请公布号 JPH09200225(A) 申请公布日期 1997.07.31
申请号 JP19960009573 申请日期 1996.01.23
申请人 NEC ENG LTD 发明人 HORAGE TOSHIO
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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