| 摘要 |
PROBLEM TO BE SOLVED: To obtain a PLL system in which high speed locking is attained and the transient characteristic of the loop is stable by varying the control sensitivity of a voltage controlled oscillator (VCO) with a control voltage and increasing the control sensitivity at locking. SOLUTION: A control input (d) of a VCO 4 connects to a drain D of a FET 6 being a switching element and connects to ground via a drain/source of the FET 6 when the FET 6 is conductive. A gate G of the FET 6 is controlled by an output of an external signal input interruption detection circuit 8 to set forcibly the control input (d) of the VCO 4 to an earth level. An external signal input interrupt detection circuit 8 is made up of an interrupt period detector 81 that detects interruption of an input signal 1a to generate a detection signal (b) and a monostable multivibrator 82 triggered at the end of detection period and generating a pulse signal (c) for a prescribed period. The pulse signal (c) is a gate signal of the FET 6. The control sensitivity K(Δf/ΔVc ) differs on the boundary of the control voltage V1, and the locking speed in set higher by increasing the sensitivity K in a region where frequencies are lower than the frequency corresponding to the signal V1. |
