发明名称 RELIABILITY ESTIMATION TEST METHOD OF SEMICONDUCTOR DEVICE, AND ELEMENT FOR ESTIMATION WHICH IS USED IN THE METHOD
摘要 PROBLEM TO BE SOLVED: To enable effectively dissipating the heat generated in viahole parts and an upper and lower double layer wiring when electromigration of the viaholes is estimated, by dissipating the heat with metal layers buried and formed in interlayer insulating films between a plurality of viaholes. SOLUTION: A lower wiring layer 3, an interlayer insulating film 4 formed on the lower wiring layer 3, an upper wiring layer 6 formed on the interlayer insulating film 4, and a plurality of viaholes 7 which connects the upper wiring layer 6 to the lower wiring layer 3 by penetrating the interlayer insulating film 4 are formed. In the case that estimation of electromigration is performed by using the above element for estimating electromigration(EM), measurement of EM estimation is performed while heat is dissipated with metal layers 5 buried and formed in the interlayer insulating films 4 between a plurality of the viaholes 7. For example, the metal layers 5 are formed in a lattice type pattern wherein a plurality of the viaholes 7 are positioned between lattice points.
申请公布号 JPH09199563(A) 申请公布日期 1997.07.31
申请号 JP19960026133 申请日期 1996.01.19
申请人 NIPPON STEEL CORP 发明人 SASAKI KAZUHISA
分类号 G01R31/26;H01L21/66;H01L23/36;(IPC1-7):H01L21/66 主分类号 G01R31/26
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