| 摘要 |
PROBLEM TO BE SOLVED: To shorten the processing delay time of a large capacity time switch (TSW) circuit by removing a delay at the time of cascade-connecting switch circuits each of which is combined by a TSW circuit and a space switch(SSW) circuit. SOLUTION: In the large capacity TSW circuit, addresses to be read out from read-only memories (ROMs) constituting time setting circuits 12 on respective stages are set up as follows. Namely the final stage is set up as a 1st stage, an address '0' is set up in the ROM constituting the time setting circuit 12 on the final stage, an address '1' is set up in the ROM constituting the time setting circuit 12 on the 2nd stage from the final stage and an address 'i-1' is set up in the ROM constituting the time setting circuit 12 on the i-th stage from the final stage. Thereby the phases of data read out from all the TSW circuits coincide with that of data read out by a final stage TSW circuit 1-2 at the time of inputting the data to a final stage SSW circuit 2-2. Consequently the input of the final stage SSW circuit 2-2 is allowed to coincide with the frame phase of the final TSW circuit 1-2. |
