发明名称 TESTING CIRCUIT AND DIGITAL IC INCORPORATING THE TESTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make it possible to measure the frequency locked by PLL in a short time and to simplify a measuring system by counting PLL operation signals by each equal period from a different time point and comparing to detect the counted result. SOLUTION: Counters A and B count signals S output from a PLL circuit 11. The counter A counts the fetched signals from the circuit 11 for the time of a high level of a counter enable signal CE, and outputs the number to counters QAO to QAn. The counter B counts the fetched signals from the circuit 11 for time of the low level of the signal CE, and outputs the number to counters QAO to QAN. In this case, n is natural number, and (n+1) becomes bit number. A comparator 13 compares the counted results of the counters A with B in the counting time. A decoder 14 fetches the decision pulse DP from the comparator 13, reads the outputs of the counters A and B, and outputs the result.
申请公布号 JPH09197024(A) 申请公布日期 1997.07.31
申请号 JP19960005876 申请日期 1996.01.17
申请人 TOSHIBA AVE CORP;TOSHIBA CORP 发明人 SUGIZAKI KAORU;ASAMI SHUJI;YABE YUKIHIKO
分类号 G01R31/316;G01R31/28;H03L7/08 主分类号 G01R31/316
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