| 摘要 |
PROBLEM TO BE SOLVED: To design a lock range and stability independently by using a fixed frequency oscillator in the digital PLL circuit. SOLUTION: An output of a digital PLL circuit is obtained by gating an output signal of a fixed frequency oscillator 7 based on an output signal of a voltage controlled oscillator 2. Since the digital PLL circuit is operated an oscillated frequency fv of the voltage controlled oscillator 2 from an oscillated frequency fout of the fixed frequency oscillator 7, the locked range of the frequency is a variable range of the voltage controlled oscillator 2 and selected independently of an output frequency of the PLL circuit. Furthermore, the stability of the frequency depends on the fixed frequency oscillator 7 and the voltage controlled oscillator 2 and the stability of the voltage controlled oscillator 2 is improved in comparison with that of a conventional system. |
