发明名称 FUKIHATSUSEIHANDOTAIMEMORISOCHI
摘要 <p>PURPOSE:To prevent an erroneous erasing in a reading action by executing an erasing action by keeping the drain and the source of a NAND cell in a floating state and giving an H level potential to a control gate. CONSTITUTION:A NAND cell is composed by connecting plural memory cells serially, and this kind of NAND cell is matrix-arranged. For each memory cell, a floating gate 4 is formed on a substrate 1 through a first gate insulating film 3, and a control gate 6 is formed on this floating gate 4 through a second gate insulating film 5. The gate 6 of each memory cell is continuously arranged in one direction and made into a word line. For an n<+> type layer 9 to be the source and the drain of each memory cell, the memory cell is connected serially in a form in which adjoining n<+> type layers 9 hold the memory cell in common. In the cell having this NAND composition, in an erasing mode, a threshold can be prevented from being too large in a positive direction by making the layer 9 into a floating. Consequently, a stable reading can be executed without making the gate 4 in a non-selected cell extremely large at the time of reading.</p>
申请公布号 JP2635630(B2) 申请公布日期 1997.07.30
申请号 JP19870290853 申请日期 1987.11.18
申请人 TOSHIBA KK 发明人 INOE SATOSHI;SHIRATA RIICHIRO;MOMOTOMI MASAKI;NAKAYAMA RYOZO;KIRISAWA RYOHEI;IWATA YOSHIHISA;MASUOKA FUJIO;ITO YASUO
分类号 G11C17/00;G11C16/04;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C17/00
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