| 摘要 |
A floating point addition and subtraction circuit comprises a comparison subtraction circuit (10) receiving two operands to be processed for making a comparison in the size between their exponent parts so to subtract the smaller exponent part from the larger one, said comparison subtraction circuit providing the comparison result and the subtraction result; a mantissa selecting circuit (20) and a shift circuit (30) for aligning the mantissa of the operand; a trailing zero counting circuit (50) for counting the number of zeros successively positioned in the high order direction from the least significant bit of the mantissa of the operand having the smaller operand; a comparator circuit (51) for making a comparison between the counting result and the subtraction result by the comparison subtraction circuit, thereby to detect a sticky bit according to the comparison result; and an absolute value addition and subtraction arithmetic circuit (60), receiving the mantissas of the two operands having been aligned and the detected sticky bit, for performing addition or subtraction operation on operand. <IMAGE> |
