| 摘要 |
A frequency difference detection apparatus includes a first PLL, a second PLL, a first phase difference detection unit, a second phase difference detection unit, a phase difference processing unit, and a frequency difference detection unit. The first PLL detects a phase difference between an input clock and an output clock in response to the input clock and performs control to gradually suppress the detected phase difference to zero. The second PLL detects a phase difference between the input clock and an output clock in response to the input clock and performs control to suppress the detected phase difference to zero at a speed higher than that of the first PLL. The first phase difference detection unit detects a phase difference between the input clock and the output clock from the first PLL. The second phase difference detection unit detects a phase difference between the input clock and the output clock from the second PLL. The phase difference processing unit processes a detection of a difference between the phase differences detected by the first and second phase difference detection units. The frequency difference detection unit detects a frequency difference between the input clock and a reference frequency from a detection output from the phase difference processing unit.
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