发明名称 Power management apparatus and method
摘要 A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.
申请公布号 AU1355997(A) 申请公布日期 1997.07.28
申请号 AU19970013559 申请日期 1996.12.27
申请人 INTEL CORPORATION 发明人 JAMES P KARDACH;CHIH-HUNG CHUNG;JASON ZILLER
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
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