| 摘要 |
The apparatus includes a control circuit (AS) through which a signal (Uontgr) to release the lock is fed to its gate. Another input to the gate is fed from a free running oscillator (OSC). The gate output operates a Darlington pair transistor (T1) in series with the solenoid (L1). The oscillator output is also fed via buffer inverters to a reactive time acceleration circuit (RTV). Successive pulses from the oscillator are used to switch the reactive current from an inductor (L2) into a capacitor (C1). The capacitor charges up to a voltage, e.g. 42 volts, which is several times higher than the 9 volt d.c. supply. The series transistor (T1) then stops conducting and the capacitor is discharged into the solenoid coil.
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