SCALABLE MULTI-PROCESSOR ARCHITECTURE FOR SIMD AND MIMD OPERATIONS

摘要

A multiprocessor device capable of operating in both MIMD and SIMD modes which include an array of parallel processor elements (1) connected via link ports on each element (39-41). A multiplexing means (3) is provided for dynamically configuring the connection topology between link ports so that a direct connection (101, 103) can be made between any two processor elements (39-41). Local dual-ported memory (23-26) is associated with each processor element in the array (1) and is connected through a first port to its associated processor element and through a second port to a multidimensional DMA controller (7). The DMA controller (7) transfers data autonomously between the processor elements (1) and global resources (11, 13), including a global memory (11). For SIMD mode operations, the DMA controller broadcasts duplicate instructions to the dual-ported memory associated with each processor element, and the instructions are executed by each processor element (39-41) in synchrony.