Reduction of phase locking in digital analysers or oscilloscopes

摘要

The process for reducing display locking in electronic oscilloscopes and analysers during the acquire cycle involves selecting the time delay between each acquire cycle randomly. Each acquire cycle is followed by a discharge cycle, which is then followed by the variable time delay period. A typical device would have two acquire memories and the following sequence would be used: Storage of a first data series, wait until a trigger event, processing of the first acquired data, selection of a time delay, storage of a second series of acquired data, delay until a second trigger, processing of the second data series and repetition of the whole cycle.