| 摘要 |
Briefly, in accordance with one embodiment of the invention, an integrated circuit is characterized in that the integrated circuit comprises a refined timing recovery circuit (e.g., 200) for retiming a recovered data signal derived from a received data pulse. The refined timing recovery circuit (e.g., 200) comprises a data pulse edge detector (e.g., 250), the edge detector (e.g., 250) being adapted to be coupled to an oversampling clock having a mutually timed series of clock pulses at a substantially predetermined frequency. The edge detector (e.g., 250) is further adapted to sense the next clock pulse edge having closest temporal proximity after a selected received data pulse edge. In accordance with yet another embodiment, a method of reducing the phase quantization error of a recovered data signal derived from a received data pulse by sampling with digital clock pulses at a first substantially predetermined frequency is characterized in that the method comprises the steps of sampling the received data pulse with digital clock pulses at a second substantially predetermined frequency so as to sense the next clock pulse edge of the digital clock pulses in closest temporal proximity after a selected edge of the received data pulse, the second substantially predetermined frequency exceeding the first substantially predetermined frequency; and retiming the recovered data signal substantially in accordance with the sensed next clock pulse edge. <IMAGE> |
