| 摘要 |
PROBLEM TO BE SOLVED: To provide the clock generating circuit which regenerates a system clock small in circuit scale and high in precision. SOLUTION: The clock generating circuit consists of a clock oscillation element 101, 1st and 2nd delay lines 102 and 103, 1st and 2nd clock phase detecting circuits 104 and 105, 1st and 2nd clock selectors 106 and 107, a circuit delay correcting circuit 108, and a peak detecting circuit 109. Once the peak detecting circuit 109 detects a synchronizing signal 201 with a constant period, the 1st clock phase detecting circuit 104 selects the phase clock which is closest to and before a next synchronizing signal 206 out of plural phase clocks 207 outputted from the 1st delay line 102. The 1st clock selector 106 outputs the delay-corrected phase clock to the 2nd delay line 103. The 2nd clock phase detecting circuit 105 selects and outputs a system clock which is phase-locked to the synchronizing signal 206 when plural phase clocks 208 having divided phases of one tap are outputted. |
