| 摘要 |
PROBLEM TO BE SOLVED: To configure a frame aligner whose input/output buffer is integrated with a processor at an output side. SOLUTION: Input data 1 are received while being timing-controlled by an input synchronizing signal 5. Furthermore, output data are controlled for its timing by a output synchronizing signal 6. A monitor circuit 7 monitors deviation in phases of both the synchronizing signals 5, 6 and a matching processing circuit 9 is operated when the phase shift is changed by a prescribed phase or over. When the period of the output synchronizing signal is shorter, data transferred just before from a buffer memory 3 are transferred in duplicate and when the output synchronizing signal is longer in the period, data are skipped for reading once. |
