发明名称 CLOCK SKEW ADJUSTING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To highly precisely adjust a clock skew through the use of a phase locked loop. SOLUTION: The clock skew circuit compensates the input delay of a clock from a clock driver 6 and outputs the clock to a synchronism circuit 8a. A phase locked loop 1a outputting the clock adjusted so that clock input and feedback input have decided phases is provided. An inversion circuit 2a inverting and outputting an input signal is inserted into a feedback path feeding back the clock output of the phase locked loop 1a to feedback input.</p>
申请公布号 JPH09190239(A) 申请公布日期 1997.07.22
申请号 JP19960003035 申请日期 1996.01.11
申请人 FUJITSU LTD 发明人 MITSUISHI KAZUYUKI
分类号 G06F1/10;(IPC1-7):G06F1/10 主分类号 G06F1/10
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