SIMULATOR FOR VERIFICATION OF POLYPHASE CLOCK INPUT LOGIC CIRCUIT,申请号JP19960002811-传众专利搜索

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发明名称	SIMULATOR FOR VERIFICATION OF POLYPHASE CLOCK INPUT LOGIC CIRCUIT
摘要
申请公布号	JPH09190461(A)	申请公布日期	1997.07.22
申请号	JP19960002811	申请日期	1996.01.11
申请人	NEC ENG LTD	发明人	KAWAGUCHI MINORU
分类号	G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F17/50
代理机构		代理人
主权项
地址

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