发明名称 SELECTIVE CALLING RECEIVER
摘要 PROBLEM TO BE SOLVED: To simply attain address collation even at the time of using a communication system transmitting plural pieces of address data of different address lengths. SOLUTION: In the decoder part 54 of a pager, the plural pieces of address data of different address lengths are stored in an address register 151. When the coincidence of the first word of a long address is obtained by comparing address data of received data and address data on a released state side equivalent to the first word by an address comparing circuit 156, a state switch control circuit 152 executes state update so, that the circuit 156 is provided with address data of a shifted state side equivalent to a second word from the address register 151 to compare concerning the second word. At the time of obtaining coincidence concerning the second word as well, an AND gate 158 output-processes a coincidence signal CNT 2 '1' to a data processing part 159 and CPU 51.
申请公布号 JPH09191481(A) 申请公布日期 1997.07.22
申请号 JP19960020556 申请日期 1996.01.10
申请人 CASIO COMPUT CO LTD 发明人 YAMAZAKI TATSUO
分类号 H04Q7/16;(IPC1-7):H04Q7/16 主分类号 H04Q7/16
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