发明名称 Method to form a capacitor having multiple pillars for advanced DRAMS
摘要 A method of fabricating a capacitor having multiple pillars is presented. The invention uses an oxidized hemispherical grain silicon (HSG-Si) layer as a masking layer, in a series of masking steps, to form pillarets on a storage electrode. The method begins by forming a storage electrode having a connection to an active area on the substrate. Next, a cap insulation layer and a cap polysilicon layer are formed over the storage electrode. The cap polysilicon layer has grains and has grain boundaries between the grains. The cap polysilicon layer is oxidized thus forming a thicker oxide layer at the grain boundaries. The oxide layer is dry etched exposing the cap polysilicon layer and leaves a grain boundary oxide covering the grain boundaries. Next, the exposed cap polysilicon layer is etched using the grain boundary oxide as a mask forming a plurality of cap polysilicon layer pillarets. The grain boundary oxide is then removed. Then the cap insulation layer is etched using the cap polysilicon layer pillarets as a mask forming cap oxide pillarets. The cap polysilicon layer pillarets are then removed. The storage electrode node is dry etched using the cap oxide pillarets as a mask forming storage electrode pillarets. The cap oxide pillarets are removed. A capacitor dielectric layer and top plate electrode are formed over the storage electrode pillarets and the storage electrode to complete the capacitor.
申请公布号 US5650351(A) 申请公布日期 1997.07.22
申请号 US19960585033 申请日期 1996.01.11
申请人 VANGUARD INTERNATIONAL SEMICONDUCTOR COMPANY 发明人 WU, SHYE-LIN
分类号 H01L21/02;H01L21/8242;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 主分类号 H01L21/02
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