发明名称 Logic simulation method and logic simulator
摘要 A method is disclosed to execute an event driven logic simulation to check the function of a logic circuit, by using a logic simulator. The logic simulator includes at least one data base and a processing unit having a dummy element synthesizer. The dummy element is a tool for detecting changes in signals at a target cell or a target terminal. At the time that the logic simulation starts, the dummy element synthesizer produces the dummy element defining data, referring to or based on information stored in the data base, and combines the dummy element defining data and the logic circuit design data. Thus, for example, timing simulation at a target cell in the logic circuit or the check of the number of times of changes in signals at a target output terminal of the logic circuit, is executed during the event driven logic simulation.
申请公布号 US5650947(A) 申请公布日期 1997.07.22
申请号 US19950377404 申请日期 1995.01.24
申请人 FUJITSU LIMITED;FUJITSU VLSI LIMITED 发明人 OKUMURA, TAKAAKI
分类号 G06F17/50;(IPC1-7):G06F17/00 主分类号 G06F17/50
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