| 摘要 |
A shift register having multiple cascaded stages (n-1, n, n+1), wherein each stage n comprises an output at a node D and is connected to the output of stage n-1 and the output of stage n+1, and first and second clock signals ( phi 1, phi 2), said stage comprising a semiconductor device (MN2) switching the output n between high and low values of clock signal phi 1, and the first semiconductor device being controlled by the potential of a node G which is in turn connected to the output of the previous stage (n-1) via a semiconductor device (MN1) controlled by the output of stage n-1, to a negative potential (V-) via a third semiconductor device (MN3) controlled by the output of stage n+1, and to the second clock signal phi 2 via a capacitor (C2), and comprising a capacitor (C3) mounted between node G and the output of stage n+1. Said shift register may be used in LCD drivers.
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