| 摘要 |
<p>A system (10) for distributing synchronous clock signals includes a set of spatially distributed deskewing stages (16(1)-16(N)). Each stage includes matching adjustable first and second delay circuits (20A(1), 20B(1)) and phase lock loop controller (22). Matching pairs of transmission lines (18A, 18B) interconnect successive stages of the set. One transmission line (18A) of each pair connects the output of the first delay circuit (20A) of each stage to the input of the first delay circuit (20) of a next stage of the set. The other transmission line (18B) of the pair connects the input of the second delay circuit (20B) of the stage to the input of the first delay circuit (20A) of the next stage. When the first delay circuit (20A) of the first stage of the set receives an input reference clock signal (CLKA), that reference clock signal propagates through all the first delay circuits (20A) of each stage in succession.</p> |
